An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM) devices.
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 102 and an access transistor or transfer device 101. For each cell 100, one side of the storage capacitor 102 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 102 is connected to the drain of the transfer device 101. The gate of the transfer device 101 is connected to a word line 104. The source terminal of the transfer device 101 is connected to a bit line 103. With the memory cell 100 components connected in this manner, it is apparent that the word line 104 controls access to the storage capacitor 102 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line 103 to be written to or read from the storage capacitor 102. Thus, each cell 100 contains one bit of data (i.e., a logic “0” or logic “1”).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in a comparand register) against an entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits that maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicates whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).
Once information is stored in a CAM memory location, the information may be found by comparing every bit of memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, a local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which the desired data is stored (or one of such addresses if more than one address contained matching data). Thus, with a CAM, the user supplies the data and gets back the address if there is a match found.
FIG. 2 is a circuit diagram showing a conventional DRAM-based CAM cell 200 that includes two one-transistor DRAM cells 210a, 210b and a four-transistor comparator circuit 220 made up of transistors Q2, Q3, Q5 and Q6. The DRAM cells 210a, 210b are used to store values in the CAM cell 200. Generally, the content of the first DRAM cell 210a is the logical complement of the content of the second DRAM cell 210b. However, the cells 210a, 210b may also store the same values, i.e., “1”, “1”, or “0”, “0”, when so desired.
The first DRAM cell 210a includes transistor Q1 and capacitor CA, which combine to form storage node A that receives a data value from bit line BL1 at node U during write operations, and applies the stored data value to the gate terminal of transistor Q2 of the comparator circuit 220. Transistor Q2 is connected in series with transistor Q3, which is controlled by a data signal transmitted on data line D1, between a match line M and a discharge line D. The second DRAM cell 210b includes transistor Q3 and capacitor CB, which combine to form storage node B that receives a data value from bit line BL2 at node V, and applies the stored data value to the gate terminal of transistor Q5 of the comparator circuit 220. Transistor Q5 is connected in series with transistor Q6, which is controlled by a data signal transmitted on inverted data line Dl#, between the match line M and the discharge line D.
FIG. 3 is a block diagram of a portion of a CAM device 300 that includes a plurality of CAM cells such as the CAM cell 200 illustrated in FIG. 2. For purposes of simplicity, only a portion of the CAM device 300 is illustrated in FIG. 3. In particular, some well known components such as e.g., the previously discussed comparand register, control logic, and input/output logic are not illustrated merely to simplify FIG. 3. The CAM device 300 includes two arrays 310a, 310b of CAM cells 200. Each array 310a, 310b includes its own bit lines (i.e., BL11–BL16 for the first array 310a, BL21–BL26 for the second array 310b) and word lines (i.e., WL11–WL13 for the first array 310a and WL21–WL23 for the second array 310b). Each word line WL11–WL13, WL21–WL23 is also coupled to a respective word line driver 320a, 320b. Similarly, each bit line BL11–BL16, BL21–BL26 is also coupled to respective bit line drivers (not illustrated). The CAM device 300 also includes a plurality of sense amplifiers 330. Each sense amplifier 330 is coupled to the CAM cells 200 connected to two different bit lines (e.g., bit lines BL11, BL21) from two different arrays 310a, 310b. This type of architecture, where a sense amplifier is coupled to bit lines from different arrays, is generally known as an open bit line architecture.
One of the drawbacks associated with DRAM cells is that the charge on the storage capacitors may naturally decay over time, even if the capacitors remain electrically isolated. Thus, DRAM cells require periodic refreshing. Additionally, refreshing is also required after a memory cell has been accessed, for example, as part of a read operation.
In DRAM-based devices, refresh commands are issued periodically to keep the contents of the DRAM memory array maintained at their previously stored values. The refresh operations have the effect of restoring charges lost from DRAM cells due to leakage currents. Refresh operations are also essential for ensuring that data in the DRAM memory is not corrupted over time. For proper DRAM operation, the device adheres to minimum operating specifications and maintains a periodic interval for issuing refresh commands.
Refresh commands may be issued explicitly to the DRAM-based device from another device such as e.g., a memory controller. Refresh operations may also be internally generated during idle cycles, with the controller concurrently ensuring that a sufficient number of idle cycles are interspersed in the command stream to meet the device's refresh requirements. This is known as a “self-refresh.”
Although refreshes allow DRAM memory to retain previously stored values, soft-errors and coupling defects can still occur that would falsely toggle a stored bit. If this erroneous toggling has occurred, future refresh operations would refresh the false value. One method of mitigating the problem of false toggling of stored data bits includes storing parity bits with the data. The memory array is periodically parity-scanned to determine if any errors have occurred. Parity-scanning may be performed internally whenever there are idle cycles. System hardware running in the background monitors the command stream to see when it can insert a parity-scan command. However, unlike refresh operations, parity-scanning is typically performed on a best-effort policy (as opposed to all inclusive policy). This means that all rows may not have been scanned by the end of the parity-scan time interval.
Accordingly, there is a desire and need to coordinate refresh and parity-scan operations in a DRAM-based device.